NYCU RISCV32 Core Design

Description

Contents:

• Overview
  • Description
  • Stages
• Instruction Fetch Stage
  • Branch Predictor
• Execute Stage
  • MUL/DIV
  • FPU
  • ALU
• Memory Stage
  • LSU (Load Store Unit)
  • MMU (Memory Management Unit)
  • Dcache
  • Dcache_axiBus_bridge
  • I cache
  • Icache_axiBus_bridge
  • cpu_axiLite_bridge
  • Memory & Peripheral Related Diagram
• other modules
  • CSR
  • CSRFile